1. Field of the Invention
The present invention relates to a thin film transistor array substrate and a manufacturing method thereof, and more particularly, to a thin film transistor array substrate and a manufacturing method thereof with reduced static electricity.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance using an electric field to display a picture. To this end, the LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the cells of the liquid crystal panel. Specifically, the liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate opposed to each other. A spacer is positioned between the thin film transistor array substrate and the color filter array substrate to keep a constant cell gap, and a liquid crystal is filled in the cell gap.
The thin film transistor array substrate includes gate lines, data lines, thin film transistors, pixel electrodes, and alignment films. Each thin film transistor serves as a switching device for a respective intersection between a gate line and a data line. A pixel electrode with a corresponding alignment film coated thereon is formed for each liquid crystal cell and connected to the thin film transistor. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel voltage signal fed to the data line in response to a scanning signal fed to the gate electrode of the thin film transistor. The color filter array substrate includes color filters formed for each liquid crystal cell, a black matrix for dividing the respective color filters and for reflecting an external light, a common electrode for commonly applying a reference voltage to the liquid crystal cells, and an alignment film coated on the common electrode. The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter array substrate individually, joining them together, injecting a liquid crystal between the two substrates and sealing the resultant panel.
The thin film transistor array substrate passes a signal inspection process for detecting line defects, such as a short or a breakage of signal lines, and thin film transistor defects after the manufacturing process. For the signal inspection process, the thin film transistor array substrate is provided with an odd shorting bar and an even shorting bar connected with the lines being divided into odd lines and even lines for each of the gate lines and data lines. Specifically, an inspection of the gate lines is made using a gate odd shorting bar commonly connected to the odd gate lines and a gate even shorting bar commonly connected to the even gate lines. Similarly, an inspection of the data lines is made by a data odd shorting bar commonly connected to the odd data lines and a data even shorting bar commonly connected to the even data lines.
For instance, as shown in FIG. 1, the thin film transistor array substrate having a data shorting bar includes a thin film transistor 5 provided at each intersection of gate lines 1 and data lines 3. A pixel electrode connected to the thin film transistor 5, and a storage capacitor 17 is formed at an overlapping portion between the pixel electrode 15 and the pre-stage gate line 1. An array area has a gate pad portion (not shown) connected to the gate line 1 and a data pad portion 31 connected to the data line 3. An odd shorting bar 8 is commonly connected, via the data pad portion, to the odd data lines 2, and an even shorting bar 6 is commonly connected to the even data lines 4.
The gate line 1 intersects the data line 3 with a gate insulating film therebetween to provide electrical insulation. The thin film transistor 5 provided at each intersection of the gate lines 1 and the data lines 3 includes a gate electrode 7 connected to the gate line 1, a source electrode connected to the data line 3, a drain electrode 11 connected to the pixel electrode, and an active layer (not shown) overlapping with the gate electrode 7 and forming a channel between the source electrode 9 and the drain electrode 11. The active layer usually extends along the data line 3. On the active layer, an ohmic contact layer is provided at an area excluding a channel portion. Such a thin film transistor 5 allows a pixel voltage signal from the data line 3 to be applied into the pixel electrode 15 and then sustained in response to a scanning signal applied to the gate line 1.
The pixel electrode 15 is connected, via a first contact hole through a protective film (not shown) to the drain electrode 11 of the thin film transistor 5. The pixel electrode 15 generates a potential difference with respect to the common electrode provided at the upper substrate (not shown) by the charged pixel voltage. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate due to a dielectric anisotropy and transmits a light inputted, via the pixel electrode 15, from a light source (not shown) that radiates toward the upper substrate.
The storage capacitor 17 has a pre-stage gate line 1, a storage electrode 19 overlapping the gate line 1 with the gate insulating film therebetween, and a pixel electrode 15 overlapping the storage electrode 19 with the protective film therebetween and connected via a second contact hole 21 through the protective film. The storage capacitor 17 allows a pixel voltage charged in the pixel electrode 15 to be stably maintained until the next pixel voltage is applied.
The data line 3 is connected, via a data link 23 and a data pad portion 31, to the data driver while the gate line 1 is connected, via a gate link and a gate pad portion, to the gate driver. The data pad portion 31 includes a data pad 25 extended, via the data link 23 from the data line 3, and a data pad protection electrode 27 connected, via a third contact hole 29 passing through the protective film, to the data pad 25.
In the data shorting bar arrangement, an odd shorting bar 8 is commonly connected, via the data pad portion 31, to odd data lines 2 while an even shorting bar 6 is commonly connected, via the data pad portion, to even data lines 4. The odd shorting bar 8 is formed from a source/drain metal layer along with the data lines 3. The even shorting bar 6 is formed from a gate metal layer to provide insulation-against the odd data lines 2 crossing it. As shown in FIG. 2, the even shorting bar 6 formed from the gate metal layer is connected, via a contact electrode 10 formed over a fourth contact hole 12, to the even data lines 4 formed from a source/drain metal layer. When the thin film transistor array substrate is completed, a defect inspection of the data line 1 is made with the aid of the odd shorting bar 8 and the even shorting bar 6. Then, the data shorting bars 6 and 8 are cut along a scribing line between the even shorting bar 6 and the data pad portion 31.
FIG. 2 is a sectional view of the data shorting bar area taken along line I-I′ and line II-II′ in FIG. 1. The even shorting bar 6 formed from a gate metal layer is provided on the lower substrate 14, and the gate insulating film 16 is provided thereon. The odd data lines 2, the even data lines 4 and the odd shorting bar 8 formed from a source/drain metal layer are provided on the gate insulating film 16, and the protective film 18 is provided thereon. The contact hole 12 through the gate insulating film 14 and the protective film 18 is formed to expose the even data lines 4 and the even shorting bar 6. The contact electrode 10 is formed over the contact hole 12 to connect the even data lines 4 and the even shorting bar 6 made from a different metal layer to each other.
Hereinafter, a method of manufacturing the data shorting bar area will be described in detail with reference to FIGS. 3A to 3D and in conjunction with a method of manufacturing the thin film transistor array substrate.
Referring to FIG. 3A, the even shorting bar 6 is provided on the lower substrate 14. The even shorting bar 6 is formed by depositing a gate metal material onto the lower substrate by a deposition technique such as sputtering or the like, and then patterning it by photolithography and etching using a first mask. Such an even shorting bar 6 is formed along with gate patterns, each of which includes the gate line 1 and the gate electrode 7, etc. within the array shown in FIG. 1. The gate metal has a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo), an aluminum group metal, or other suitable material.
Referring to FIG. 3B, the gate insulating film 16, the data lines 2 and 4 and the odd shorting bar 8 are disposed on the lower substrate 14 provided with the even shorting bar 6. The gate insulating film 16 is formed by entirely depositing a gate insulating material using a deposition technique such as plasma enhanced chemical vapor deposition or other technique. The gate insulating material is made from silicon nitride (SiNx) or silicon oxide (SiOx). Subsequently, an active layer and an ohmic contact layer within the array shown in FIG. 1 are formed by sequentially depositing an amorphous silicon layer and an amorphous silicon layer on the gate insulating film 16 and then patterning the deposited layers by photolithography and etching using a second mask.
The data lines 2 and 4 and the odd shorting bar 8 are formed by depositing a source/drain metal material onto the gate insulating film 16 using a deposition technique such as sputtering or the like and then patterning it by photolithography and etching using a third mask. The data lines 2, 4 and the odd shorting bar 8 are formed along with source/drain patterns, each of which includes the data line 3, the source electrode 9, the drain electrode 11, the storage electrode 19, the data pad 25, etc. within the array shown in FIG. 1. The source/drain metal is made from molybdenum (Mo), titanium (Ti), tantalum (Ta), a molybdenum alloy, or other suitable material.
Referring to FIG. 3C, the protective film 18 including the contact hole 12 is provided. The protective film 18 is formed by depositing an insulating material using a deposition technique such as PECVD. The protective film 18 is made from an inorganic insulating material identical to the gate insulating film 16, or an organic material having a small dielectric constant such as an acrylic organic compound, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), or the like.
The fourth contact hole 12 of the even shorting bar 6 is defined, along with a plurality of contact holes 13, 21 and 29 within the array shown in FIG. 1, by patterning the protective film 18 and the gate insulating film 16 by photolithography and etching using a fourth mask.
Referring to FIG. 3D, the contact electrode 10 is formed over the fourth contact hole 12. The contact electrode 10 is formed by depositing a transparent electrode material onto the protective film 18 using a deposition technique such as sputtering and then patterning it by photolithography and etching using a fifth mask. Such a contact electrode 10 is formed along with transparent electrode patterns, each of which includes the pixel electrode 15, the data pad protection electrode 27, etc. within the array shown in FIG. 1. The transparent electrode material is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
In such a thin film transistor array substrate, the even data lines 4 have a characteristic in that they are relatively susceptible to static electricity in the course of the manufacturing process. Specifically, each of the even data lines 4 are separate after patterning of the source/drain metal layer until formation of the contact electrode 10. In contrast, the odd data lines 2 are commonly connected with the aid of the odd shorting bar 8 formed from the same source/drain metal layer. Thus, if static electricity occurs after patterning of the source/drain metal layer, the static electricity is diffused and therefore reduced at the odd data lines 2 commonly connected by the odd shorting bar 8, thereby preventing a damage caused by the static Electricity. However, the even data lines 4 have not been provided with the contact electrode 10 and are separated until they are commonly connected by the even shorting bar 6. Therefore, if a static electricity is input to the even data lines 4 before formation of the contact electrode 10, then the thin film transistors connected to the even data lines 4 can be damaged or a defect can occur such as a insulation breakage at an intersection between the even data line 4 and the gate line or at another location.